XGATE Demo Project using the Imagecraft Compiler (7.07A)

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This demo project is a simple example of how to develop an xgate co-processor thread with the Imagecraft compiler (http://www.imagecraft.com/).  Several years ago Edward Karpicz developed a xgate macro assembler for the ICCV712 compiler and I've managed to get it working with the invaluable assistance of Joël Pétrique (http://dieseinfo.com/).  Although a linker for xgate was not implemented (7.07A is the version as I write) it is possible to utilize the xgate by carefully extracting address data from the map file and output file and feeding it back into the project for a recompile.  This demo uses the realtime interrupt (rti) peripheral to illustrate this process.   My goal with the demo is to demystify xgate programming for those already using the ICC compiler so I won't go into the details of the source code that are not specific to the xgate.  Note that the demo will function without the xgate if the XGATE define in all.h is commented out.

The hardware I use for this demo is the DEMO9S12XDT512 board that I purchased from Digikey.  This board is excellent value considering that it has an integrated USB P&E Micro bdm pod which makes programming and debugging a breeze.  The kit comes with a code limited version of the CodeWarrior C compiler however this demo will be using ICC along with the NoICE debugger.  Note that there is a standard bdm connector on the board so that you can use alternative pod/debuggers.  An important caveat with respect to NoICE is that has no ability to debug within the xgate co-processor.  Debugging xgate code with a debugger tool will require prototyping in CodeWarrior or other toolchain first.  Please correct me in the comments if I am mistaken on this or any other point.

Developing xgate threads with ICC assumes that the reader has at least a passing knowledge of the paged addressing scheme used in Freescale HC12 microcontrollers.   Unfortunately the Freescale documentation seems to be written for exclusively for engineers which makes understanding of this concept difficult for hobbyists and those new to the chip.  My own understanding is incomplete so I will not offer a definitive discussion of paging here.  In short, the HC12 architecture is based on the HC11 but with addressing beyond 64Kbyte via the use of paged windows.   Each window (flash, ram, eeprom) has an associated register that determines where this area resides in the global memory space.   The global memory space for the S12X micros is half of the 24 bit range (8Mbyte) though only a small fraction of that area is implemented.  I have no love for this addressing scheme but I can understand why it was adopted since HC11 was the most popular microcontroller of its time.

In my humble opinion Freescale should provide additional documentation that makes it easier for ordinary people to understand the memory architecture.  It seems to me that the intended user base of HC12 are either engineers with legacy HC11 experience or new users who can ignore the complexity of paged addressing because it is hidden inside the CodeWarrior compiler that Freescale sells for a hefty price. 

The demo is without copyright or guarantee.

AttachmentSize
[file] xgate_rti_demo.zip
Archive of complete ICC project
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