HC9S12

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The following pages are code examples for the Freescale 9S12 microcontroller. The C compiler I use is ICC12. These pages are without copyright or guarantee

Erika OSEK

The DEMO9S12XSFAME board can be programmed with the P&E Multilink if the BDM connector (J106) is populated with a 6 pin header and the J202 jumpers are removed.

64-bit Square Root

Optimized for the architecture of the HC12.  Worst case execution time is approximately 24000 cycles (.6msec on a 40MHz xgate part). 

32x32 bit divide

The ICC12 library 32-bit by 32-bit divide requires more than 2500 cycles.  It is your typical shift-subtract algorithm that does not make use of the efficiencies of the divide routines in the HC12 instruction set.  The following function executes in 314 cycles or less.  Random tests have run successfully since May 2010.  Note that the arguments of uldiv must point to separate memory locations (ie: uldiv(&a, &b, &a) will cause an error).

32x32 bit multiply

The ICC12 library doesn't supply a 64 bit result for it's long multiply.   This routine is an extension of the existing 32x32 library function and requires the user to define a uint64 type.  For a 9S12 running at 24MHz the function executes in 5.5usec.

ATD Example

This implementation of the S12ATD10B8C module is suitable for a system requiring a single ATD channel only. Reads automatically kick off a new sequence of eight conversions of the defined channel with the result being the average of those eight conversions. The maximum rate for updated data is approximately 20KHz.

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